Magnetic core memory is a RAM (Random Access Memory) that was developed at MIT by Jay Forrester in 1951.
Ferrite core memory consists of mats in which a matrix of ferrite cores are arranged. Through every ferrite core passes several wires to magnetise the core in one of the two possible directions, and to read the direction of the magnetisation. Depending the direction of the magnetisation the electronics interprets this as a logic 1 or 0.
Each core is threaded by 3 wires, which provide the possibility to select and to switch the magnetisation in the core.
The X-axis read/write wire passes through the core in each horizontal row, the Y-axis read/write wire passes through the core in each vertical row.
A sense/inhibit wire passes through all the cores in one mat.
The figure at the right shows a single core with an X wire, a Y wire and the sense/inhibit wire passing through the core. If a current of magnitude Im/2 flows in both the X and Y wire in the direction indicated, a magnetic field is produced in the core.
The flux lines of the magnetic field encircle the core in the direction shown by the arrows.
If the direction of the current flow is reversed, the magnetic field also reverses direction. This change in flux induces a voltage pulse in the sense wire that can be detected by a sense amplifier.

• This effect causes what is called "destructive reading". When the core holds a logic 0 and a current is sent through both the X and Y wire, nothing changes and the electronics interprets the state of the core as a logic 0. However, if the core holds a logic 1 and the current is sent through both the X and Y wire, the flux changes, effectively changing the state of the core from a logic 1 into a logic 0. Since the flux change induces a voltage pulse in the sense wire, the electronics interprets the previous state of the core as a logic 1.
  The electronics will do a read/write cycle to correct the destructive read sequence and store back the logic 1 into the core.
• Core memory is non-volatile so it will not loose its data when the power is removed. Logic in the memory controller prevents the change of the data stored in the core unless the supply voltages are at the correct level.

These are the steps in a write cycle.

1. A (destructive) read cycle must have preceded a write cycle to set the bit to 0.
2. The address of the memory location to be written is decoded into a X and a Y wire.
3. Only one X and Y wire is driven with a pulse of current. The pulse is in the opposite direction to the read pulse.
   The sum of the current through both wires is sufficient to magnetise the core.
4. All other bits will at worst receive only the half of the current required to change the magnetization, so they are not affected.
5. If the bit must be a logic 0, the sense/inhibit wire is driven with enough current to neutralise the effect of the X and the Y wire to keep the bit at a logic 0.
6. If the bit must change to a logic 1 the sense/inhibit wire is not driven and the X and Y wire will flip the magnetization of the core into the "1" state.

1. The address of the core to be read is decoded in a X and a Y wire.
2. Only the X and Y wire are driven with a pulse to access the core.
3. All other bits will at worst receive only the half of the current required to change the magnetization, so they are not affected.
4. If the core accessed contains a logic 0, the sense/inhibit wire will not detect a change, and the electronics will produce a logic 0.
5. If the core accessed contains a logic 1, the sense/inhibit wire detects a pulse caused by the combined pulse of the current to flip the state of the core to a logic 0, and the electronics will produce a logic 1.
6. The read cycle is always followed by a write cycle.

• Processors have instructions that do a so-called Read/Modify/Write cycle. The processor reads the memory location, changes the data (for example a simple "add 1") and then the processor writes the result back to the same location.
  Instead of wasting time with a read/write cycle (get the data) and then an other read/write cycle to write the result, a special access method is used. The processor reads the memory location and the holds the memory controlled in a paused state. After the processor has changed the data, the processor starts the second part of the write cycle to store the data.
• Core memory is not the fastest type of memory around. The latest developments allows a cycle time of 600 nSec.
  A technique called interleaving was introduced to speed up the access time for sequential memory locations. If you have two memory systems that are of the same size, then the address decoding logic can be arranged so, that every other memory location is inan other memory system. This technique doubles the speed of memory when sequential locations are accessed.

Old magnetic core technology appears to be very hot in modern Random Access Memory design!
The new design is called MRAM, Magnetic Random Access Memory. MRAM is partly based on the technology of hard disks, and partly based on DRAM, dynamic RAM.

In short, this is how MRAM operates.
Sandwiched between 2 magnetic layers, a current is used to change the polarity (1 or 0, positive or negative). Contrast this with how hard disks work (small magnetic tip on actuator). Obviously, currents are much faster and operate at speeds not determined by how fast a platter rotates. However, the polarity must still be read by some sort of magnetically sensitive device, and the speed at which it can be read limits the overall speed of the memory. Still, using currents, IBM scientists were able to bring MRAM into the realm of Random Access Memory and out of hard drive territory and achieved speeds in the low nanosecond range. Motorola labs are developing a 4 Mbit MRAM chip and say that it will go into production somewhere in 2003 or 2004. The article says that the memory retains its state when power is removed and that every bit is built of one transistor, one magnetic tunneling junction (1T-1MTJ). In a test there was no degradation in the resistance after 10 billion read-write operations. This means that MRAM is likely to exceed the numbers achieved by flash and ferroelectric memory. But MRAM is also fast with read and write times on the order of a few tens of nanoseconds. An existing 256-kbit MRAM is organized in a 16-kbit-by-16 array, and it has measured read power consumption of 24 mW at 3 volts.
As you can see in the figure the "bit line" and the "word line" quite resemble the X and Y wire of the "old" magnetic core technology.

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