ABSTRACT :
This program contains three parts CPU, TRAP and EIS tests. In the first and second parts, the program will halt on errors, in part three,
the EIS test, when an error is detected, the ERROR-PC and TEST-# will be typed then the program will continue execution.
Part 1 the CPU checks out the basic PDP11 instructions in every addressing mode with various data patterns.
Part 2 tests all trap instructions, trap overflow conditions R6, interrupts, the reset and wait instruction.
Part 3 tests the EXTENDED INSTRUCTION SET, the ASH, ASHC, MUL and DIV instruction.
HARDWARE REQUIREMENTS :
The test needs 16k of memory.
OPERATING PROCEDURES :
200 normal start
1024 restart address
The test prints : CJKDBD0 DCF11-AA DIAGNOSTIC
ERROR REPORTING:
The diagnostic responds to errors in part 1 and 2 by storing certain information in memory and halting the processor. This information can be used
by the operator to identify the error. For more infromation refer to your microfiche library.
SWITCH SETTINGS :
The initial contents of loc 176 is 000000, the user may preset this location before starting the program. You can do this by halting the CPU (use
halt switch)
deposit a 1 into 176 : @176/000000 1 <CR>
examine 176 : @176/000001<CR>
proceed @P
SW 15 =1 halt on error (part 3 only)
SW 13 =1 inhibit error typeout (part 3 only)
SW 01 =1 CIS chip set present
SW 00 =1 skip trap test
NOTES :
JKDBA0.BIC Test is changing baudrate of DLV11.
or DLV11-F with programmable baud rate.
JKDBB0.BIC Test does not run with line clock enabled.
JKDBC0.BIC Test needs update mainly for the 11/24.